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2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcomputer mitsubishi description the 32180 group is a 32-bit, single-chip risc microcom- puter with built-in flash memory, which was developed for use in general industrial and household equipment. to ac- complish high-precision arithmetic operations, it incorpo- rates a fully ieee754 compliant, single-precision fpu. this microcomputer contains a variety of peripheral func- tions ranging from two independent blocks of 16-channel a- d converters to 64-channel multifunction timers, 10-channel dmacs, 6-channel serial i/os, and 1-channel real-time de- bugger. also included are 2-channel full-can modules and jtag (boundary scan facility). with the software necessary to run these numerous peripheral functions stored in its large-capacity flash memory, this microcomputer meets the needs of application systems for high functionality, high- performance arithmetic capability, and sophisticated control. with lower power consumption and low noise characteris- tics also considered, these microcomputers are ideal for embedded equipment applications. features m32r-fpu core uses the m32r family risc cpu core (m32r family common instruction set + single-precision fpu/extended instructions) five-stage pipelined processing sixteen 32-bit general-purpose registers 16-bit/32-bit instructions implemented dsp function instructions (sum-of-products calculation using 56-bit accumulator) built-in single-precision fpu (fully compliant with ieee754 standard: four rounding modes, etc.) bit manipulation extended instructions built-in flash memory .....................1m bytes (1024k bytes) built-in flash programming boot program built-in ram ....................................................... 48k bytes pll clock generating circuit.............. built-in x 8 pll circuit oscillation stop detection function maximum operating frequency of the cpu clock type name frequency temperature range m32180f8vfp 64mhz -40c to +125c M32180F8TFP 80mhz -40c to +85c single power supply: 5 v (+ 0.5 v) or 3.3 v (+ 0.3 v) 64-channel multijunction timers (mjt) multifunction timers are incorporated that support various purposes of use. 16-bit output related timers (top) ................... 11 channels 16-bit input/output related timers (tio)............ 10 channels 16-bit input related timers (tms) ....................... 8 channels 16-bit input related up/down-timers (tid) .......... 3 channels 24-bit output related timers (tou) ................... 24 channels 32-bit input related timers (tml) ....................... 8 channels flexible configuration is possible through interconnection of timers. the internal dmac and a-d converter can be started by a timer. built-in pwm output cut function for motor control (tou) real-time debugger includes dedicated clock-synchronized serial i/o that can read and write the contents of the internal ram independ- ently of the cpu. can look up and update the data table in real time while the program is running. can generate a dedicated interrupt based on rtd com- munication. abundant internal peripheral functions in addition to the timers and real-time debugger, the micro- computer contains the following peripheral functions. dmac ............................................................. 10 channels a-d converters (sample & hold mode, disconnection de- tector assist function, injection current bypass circuit) ................................16 channels 10-bit converter x 2 serial i/o ........................................................... 6 channels interrupt controller: 32 interrupt sources, 8 priority levels wait controller full can (can specification 2.0b active)......... 2 channels virtual-flash emulation function .......... 4k bytes x 8 banks jtag (boundary scan function, mitsubishi original sdi debug function) port input threshold level select function designed to operate at high temperatures to meet the need for use at high temperatures, m32180f8vfp is designed to be able to operate in the temperature range of -40 to +125c when cpu clock oper- ating frequency = 64 mhz. M32180F8TFP is designed to be able to operate in the temperature range of ?40 to +85c when cpu clock operating frequency = 80 mhz. applications automobile equipment control (e.g., engine, abs, and at), industrial equipment system control, and high-function oa equipment (e.g., ppc)
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcomputer 2 p174/txd2 p175/rxd2 p176/txd3 p177/rxd3 p173/tin25 p172/tin24 fp mod0 mod1 excvdd vss excvcc vdde vss vcce vcc-bus p17/db15 p16/db14 p15/db13 p14/db12 p13/db11 p12/db10 p11/db9 p10/db8 p07/db7 p06/db6 p05/db5 p04/db4 p03/db3 p02/db2 p01/db1 p00/db0 vss p73/hack# p72/hreq# p71/wait# p70/bclk/wr# p43/rd# p42/bhw#/bhe# p41/blw#/ble# vcc-bus vss ad1in15 ad1in14 ad1in13 ad1in12 ad1in11 ad1in10 ad1in9 ad1in8 avss1 ad1in7 ad1in6 ad1in5 ad1in4 ad1in3 ad1in2 ad1in1 ad1in0 vref1 p82/txd0 p83/rxd0 p84/sclki0/sclko0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 p65/sclki4/sclko4 p66/sclki5/sclko5 p67 p210/to37 p211/to38 p212/to39 p213/to40 p214/to41 p215/to42 p216/to43 p217/to44 p160/to21 p161/to22 p162/to23 p163/to24 p164/to25 p165/to26 p166/to27 p167/to28 vss vcce vcc-bus p226/cs2# p227/cs3# p44/cs0# p45/cs1# p224/a11/cs2# p225/a12/cs3# p46/a13 p47/a14 p30/a15 p31/a16 p32/a17 p33/a18 p34/a19 p35/a20 p36/a21 p37/a22 vss p20/a23 p21/a24 p22/a25 p23/a26 p24/a27 p25/a28 p26/a29 p27/a30 vcc-bus vss vcce p93/to16 p94/to17 p95/to18 p96/to19 m32180f8vfp M32180F8TFP 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 package 240p6y-a(0.5mm pitches) avcc1 vss vcce p150/tin0 p151/tin1 p152/tin2 p153/tin3 p154/tin4 p155/tin5 p156/tin6 p157/tin7 p200/txd4 p201/rxd4 p202/txd5 p203/rxd5 p130/tin16/pwmoff0 p131/tin17/pwmoff1 p132/tin18 p133/tin19 p134/tin20 p135/tin21 p136/tin22 p137/tin23 p220/ctx0 p221/crx0 p222/ctx1 p223/crx1 vcce osc-vss vcnt osc-vcc xin osc-vss xout reset# p180/to29 p181/to30 p182/to31 p183/to32 p184/to33 p185/to34 p186/to35 p187/to36 p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk jtdi jtdo jtrst jtck jtms p100/to8 p101/to9/txd3 p102/to10/ctx1 p103/to11 p104/to12 p105/to13 p106/to14 p107/to15 p97/to20 p117/to7 p116/to6 p115/to5 p114/to4 p113/to3 p112/to2 p111/to1 p110/to0 p147/tin15 p146/tin14 p145/tin13 p144/tin12 p143/tin11 p142/tin10 p141/tin9 p140/tin8 p197/tin33/pwmoff2 p196/tin32 p195/tin31 p194/tin30 p193/tin29 p192/tin28 p191/tin27 p190/tin26 p127/tclk3 p126/tclk2 p125/tclk1 p124/tclk0 excvcc vss vcce vss vss vss sbi# p63 p62 p61 ad0in15 ad0in14 ad0in13 ad0in12 ad0in11 ad0in10 ad0in9 ad0in8 avss0 ad0in7 ad0in6 ad0in5 ad0in4 ad0in3 ad0in2 ad0in1 ad0in0 vref0 avcc0 vss vcce note: it is shown that the pin (signal) with which "#" sticks to the last of a pin name (signal name) is "l" active pin (signal ). pin assignment(top view) figure 1. pin layout diagram
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 3 pll clock generation circuit internal bus interface address data internal ram (48k bytes) internal flash memory (1m bytes=1024k bytes) m32r-fpu core (max. 80mhz) multiplier accumulator (32x16+56) dmac (10 channels) input/output timer (64 channels) serial i/o (6 channels) a-d converter x 2 (a-d0 : 10-bit,16 channels) (a-d1 : 10-bit,16 channels) wait controller interupt controller (8 priority levels) real-time debugger (rtd) external bus interface internal 32-bit bus input/output port 158 ports full can (2 channels) single-precision fpu (fully ieee754 compliant) internal 16-bit bus internal 32-bit bus internal power supply generation circuit (vdc) figure 2. block diagram
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 4 table 1. outline performance functional block features m32r-fpu core m32r family cpu core, internally configured in 32-bit built-in multiplier-accumulator (32 x 16 + 56) basic bus cycle m32180f8vfp: 15.625 ns (cpu clock frequency at 64 mhz, internal peripheral clock frequency at 16mhz) M32180F8TFP: 12.5 ns (cpu clock frequency at 80 mhz, internal peripheral clock frequency at 20mhz) logical address space: 4g bytes, linear general-purpose register: 32-bit register x 16, control register: 32-bit register x 6 accumulator: 56-bit external data bus 16-bit data bus instruction set 16-bit/32-bit instruction formats 100 discrete instructions in six addressing modes internal flash memory 1024k bytes rewrite durability: 100 times internal ram 48k bytes dmac 10 channels (dma transfers between internal peripheral i/os, between internal peripheral i/o and internal ram, and between internal rams) channels can be cascaded and can operate in combination with internal peripheral i/o multijunction timer 64 channels of multijunction timers. top : 16-bit output related timer, 11 channels (single-shot, delayed single-shot, and continuous) tio : 16-bit input/output related timer, 10 channels (measure clear/measure free-run/noise processing input, pwm/ single-shot/delayed single-shot/continuous output) tms : 16-bit input related timer, 8 channels (measure input) tid : 16-bit input related up/down-timer, 3 channels (fixed period, event count, up/down event count, x4 count) tou : 24-bit output related timer, 24 channels (pwm, single-shot pwm, delayed single-shot, single-shot, con- tinuous) note: functions as a 16-bit timer when in pwm or one-shot pwm mode tml : 32-bit input related timer, 8 channels (measure input) flexible timer configuration is possible through interconnection of channels using the clock bus or event bus. a-d converter 2 independent 10-bit multifunction a-d converters input 16 channels x 2 scan-based conversion can be switched between n (n = 1 to 16) channels capable of interrupt conversion during scan 8-bit/10-bit readout function available with sample & hold mode disconnection detector assist function injection current bypass circuit serial i/o 6 channels (the serial i/os can be set for synchronous serial i/o or uart. sio2, sio3 are uart mode only) real-time debugger (rtd) 1-channels dedicated clock-synchronized serial h?0080 4000 to h?0080 ffff: internal ram area can access the internal ram for read/rewrite from outside independently of the cpu, and also generate an exclu- sive-use interrupt. interrupt controller controls interrupts from internal peripheral i/os (priority can be set to one of 8 levels including interrupt disabled) wait controller controls wait when accessing external extended area (chip selects for four external extended areas each can have access extended for 0?7 wait cycles plus wait# signal entered from external source) (note1) can two channels, each having 16-channel message slots jtag boundary-scan function, built-in sdi debugger function in mitsubishi clock m32180f8vfp: cpu clock: maximum 64 mhz (for cpu, internal rom, and internal ram access) internal peripheral clock (bclk): maximum 16 mhz (for peripheral module access) external input clock (xin): maximum 8.0 mhz, built-in x8 pll circuit M32180F8TFP: cpu clock: maximum 80 mhz (for cpu, internal rom, and internal ram access) internal peripheral clock (bclk): maximum 20 mhz (for peripheral module access) external input clock (xin): maximum 10.0 mhz, built-in x8 pll circuit power supply voltage 5 v (+ 0.5 v) or 3.3 v (+ 0.3 v) [t.b.d]: single power supply voltage (the internal logic operates with 2.5 v, how- ever) operating temperature range m32180f8vfp: -40 to +125c (cpu clock 64mhz, internal peripheral clock 16mhz) (note2) M32180F8TFP: -40 to +85c (cpu clock 80mhz, internal peripheral clock 20mhz) package 0.5mm pitches / 240-pin qfp package (240p6y-a) note 1: wait cycle by the external wait# input is not received when 0wait is selected. moreover, as for all idol setup after th e wait / strike robe / recovery / lead of cs block, only operation by "nothing" setup is guaranteed when 0wait is selected. note 2: this does not mean that the microcomputer is guaranteed for continuous operation at 125c. if 125c applications are desired, please consult mitsubishi.
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 5 m32180f8vfp, M32180F8TFP port15 port16 port13 port14 port12 port4 p45/cs1# xin xout vcnt osc-vcc osc-vss p70/bclk/wr# reset# mod0 mod1 fp p220/ctx0 8 p221/crx0 p224/a11/cs2# p225/a12/cs3# p222/ctx1 p223/crx1 p226/cs2# p227/cs3# p150/tin0-p157/tin7 p160/to21-p167/to28 p180/to29-p187/to36 p190/tin26-p196/tin32 p210/to37-p217/to44 p197/tin33/pwmoff2 p130/tin16/pwmoff0 p131/tin17/pwmoff1 p132/tin18-p137/tin23 p140/tin8-p147/tin15 p124/tclk0-p127/tclk3 p93/to16-p97/to20 p100/to8 p101/to9/txd3 p102/to10/ctx1 p103/to11-p107/to15 p110/to0-p117/to7 ad1in0-ad1in15 ad0in0-ad0in15 avcc0, avcc1 avss0, avss1 vref0, vref1 p61-p63 p65/sclki4/sclko4 p66/sclki5/sclko5 p67 sbi# vcce excvcc vss p44/cs0# p43/rd# p42/bhw#/bhe# p41/blw#/ble# p71/wait# p72/hreq# p73/hack# p20/a23-p27/a30 p30/a15-p37/a22 p46/a13, p47/a14 p00/db0-p07/db7 p10/db8-p17/db15 p82/txd0 p83/rxd0 p84/sclki0/sclko0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 p174/txd2 p175/rxd2 p172/tin24, p173/tin25 p176/txd3 p177/rxd3 p200/txd4 p201/rxd4 p202/txd5 p203/rxd5 p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk jtms jtck jtrst jtdo jtdi vdde excvdd vcc-bus bus control bus control address bus address bus bus control data bus serial i/o serial i/o serial i/o serial i/o serial i/o rtd port2 port3 port21 port22 port0 port1 port17 port18 port19 port20 port7 port8 jtag port11 port10 port9 multijunc- tion timer clock reset mode can can a-d converter interrupt controller port6 8 8 8 2 5 5 8 4 6 8 8 8 2 8 7 8 13 7 2 2 3 16 16 2 2 2 4 note: it is shown that the pin (signal) with which "#" sticks to the last of a pin name (signal name) is "l" active pin (signal ). multijunc- tion timer multijunc- tion timer figure 3. pin function diagram
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 6 table 2. description of pin function (1/3) type pin name description input/output function vcce power supply - power supply (5.0v + 0.5v or 3.3 v + 0.3v). excvcc external capaci- tance connect - external capacitance connecting pin. vcc-bus bus power supply - power supply for the bus control pins (5.0v + 0.5v or 3.3 v + 0.3v). vdde ram power supply - internal ram backup power supply (5.0v + 0.5v or 3.3 v + 0.3v). excvdd external capaci- tance connect - backup power supply for the internal ram, external capacitance con- necting pin. power supply vss ground - connect all vss pins to ground (gnd). xin clock input input xout clock output output clock input/output pins. these pins contain a pll-based frequency multiply-by-8, so input the clock whose frequency is 1/8 the operating frequency. (xin input = 10 mhz when cpu clock operates at 80 mhz) bclk system clock output outputs a clock twice the externally sourced clock frequency, xin (when the internal cpu memory clock is 80 mhz, bclk output = 20 mhz). use this output when external sync design is desired. osc-vcc clock power supply - power supply to the pll circuit. connect osc-vcc to the power supply osc-vss clock ground - connect osc-vss to ground. clock vcnt pll control input this pin controls the pll circuit. connect a resistor and capacitor to this pin. reset reset# reset input this pin resets the internal circuits. these pins set an operation mode. mod0 mod1 mode 0 0 single-chip mode 0 1 expanded external mode 1 0 processor mode (boot mode) (note1) mode mod0, mod1 mode input 1 1 (do not select) flash only fp flash protect input this pin protects the flash memory against e/w in hardware. address bus a11-a30 address bus output to allow four blocks of up to 2 mb memory space each to be added externally, 20-bit address (a11-a30) is provided. a31 is not output. data bus db0-db15 data bus input/output this is a 16-bit data bus connecting to an external device. during write cycle, the microcomputer outputs bhw# or blw# to indicate the valid byte write position of the 16-bit data bus. during read cycle, the micro- computer always reads the full 16-bit data bus. transferred to the inter- nal circuit of the m32r, however, is the data at only the valid byte posi- tion. cs0#-cs3# chip select output chip select signals for external devices. rd# read output this signal is output when reading external devices. wr# write output this signal is output when writing external devices. bhw# byte high write output blw# byte low write output indicates the byte positions to which valid are transferred when writing to external devices. bhw#/bhe# and blw#/ble# correspond to the upper address side (db0-db7 effective) and the lower address side (db8-db15 effective), respectively. bhe# byte high enable output for external device access, it indicates that the upper byte data (db0- db7) is valid. ble# byte low enable output for external device access, it indicates that the lower byte data (db8- db15) is valid. wait# wait input if wait# input is low when the m32r accesses external devices, the wait cycle extended. hreq# hold request input this pin is used by an external device to request control of the external bus. the m32r goes to a hold state when hreq# input is pulled low. bus control hack# hold acknowledge output this signal indicates to the external device that the m32r has entered a hold state and relinquished control of the external bus. note 1: in boot mode, the fp pin must be at the high level.
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 7 table 2. description of pin function (2/3) type pin name description input/output function tin0 -tin33 timer input input input pin for multijunction timer to0 -to44 timer output output output pin for multijunction timer multijunction timer tclk0 -tclk3 timer clock input clock input pin for multijunction timers. avcc0, avcc1 analog power sup- ply - avcc0 and avcc1 are the power supply for the a-d0 converter and a- d1 converter, respectively. connect avcc0 and avcc1 to the power supply rail. avss0, avss1 analog ground - avss0 is the analog ground for the a-d0 converters. avss1 is the analog ground for the a-d1 converters. connect avss0, 1 to ground. ad0in0 -ad0in15 ad1in0 -ad1in15 analog input input 16-channel analog input pins for the a-d0 converter in the first block. 16-channel analog input pins for the a-d1 converter in the second block. a-d converter vref0, vref1 reference voltage input input vref0 and vref1 are the reference voltage input pin for the a-d0 converter and a-d1 converter, respectively. interrupt controller sbi# system break inter- rupt input system break interrupt (sbi) input pin of the interrupt controller sclki0/ sclko0 uart trans- mit/receive clock output or csio transmit/receive clock input/output input/output when channel 0 is in uart mode: clock output derived from brg output by dividing it by 2 when channel 0 is in csio mode: transmit/receive clock input when external clock is selected transmit/receive clock output when internal clock is selected sclki1/ sclko1 uart trans- mit/receive clock output or csio transmit/receive clock input/output input/output when channel 1 is in uart mode: clock output derived from brg output by dividing it by 2 when channel 1 is in csio mode: transmit/receive clock input when external clock is selected transmit/receive clock output when internal clock is selected sclki 4/ sclko4 uart trans- mit/receive clock output or csio transmit/receive clock input/output input/output when channel 4 is in uart mode: clock output derived from brg output by dividing it by 2 when channel 4 is in csio mode: transmit/receive clock input when external clock is selected transmit/receive clock output when internal clock is selected sclki5/ sclko5 uart trans- mit/receive clock output or csio transmit/receive clock input/output input/output when channel 5 is in uart mode: clock output derived from brg output by dividing it by 2 when channel 5 is in csio mode: transmit/receive clock input when external clock is selected transmit/receive clock output when internal clock is selected txd0 transmit data output transmit data output pin of serial i/o channel 0 rxd0 receive data input receive data input pin of serial i/o channel 0 txd1 transmit data output transmit data output pin of serial i/o channel 1 rxd1 receive data input receive data input pin of serial i/o channel 1 txd2 transmit data output transmit data output pin of serial i/o channel 2 rxd2 receive data input receive data input pin of serial i/o channel 2 txd3 transmit data output transmit data output pin of serial i/o channel 3 rxd3 receive data input receive data input pin of serial i/o channel 3 txd4 transmit data output transmit data output pin of serial i/o channel 4 rxd4 receive data input receive data input pin of serial i/o channel 4 txd5 transmit data output transmit data output pin of serial i/o channel 5 serial i/o rxd5 receive data input receive data input pin of serial i/o channel 5
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 8 table 2. description of pin function (3/3) type pin name description input/output function rtdtxd transmit data output serial data output pin of the real-time debugger rtdrxd receive data input serial data input pin of the real-time debugger rtdclk clock input input serial data transmit/receive clock input pin of the real-time debugger real-time debugger rtdack acknowledge output this pin outputs a low pulse synchronously with the real-time debug- ger?s first clock of serial data output word. the low pulse width indicates the type of the command/data the real-time debugger has received. ctx0.ctx1 transmit data output data output pin from can module. can crx0, crx1 receive data input data input pin to can module. jtms test mode input test select input for controlling the test circuit?s state transition jtck clock input clock input to the debugger module and test circuit. jtrst test reset input test reset input for initializing the test circuit asynchronously. jtdo serial output output serial output of test instruction code or test data. jtag jtdi serial input input serial input of test instruction code or test data. p00-p07 input/output port0 input/output programmable input/output port. p10-p17 input/output port 1 input/output programmable input/output port. p20-p27 input/output port 2 input/output programmable input/output port. p30-p37 input/output port 3 input/output programmable input/output port. p41-p47 input/output port 4 input/output programmable input/output port. p61-p67 input/output port 6 input/output programmable input/output port. (however, p64 is an input-only port) p70-p77 input/output port 7 input/output programmable input/output port. p82-p87 input/output port 8 input/output programmable input/output port. p93-p97 input/output port 9 input/output programmable input/output port. p100- p107 input/output port 10 input/output programmable input/output port. p110- p117 input/output port 11 input/output programmable input/output port. p124 -p127 input/output port 12 input/output programmable input/output port. p130 -p137 input/output port 13 input/output programmable input/output port. p140 -p147 input/output port 14 input/output programmable input/output port. p150 -p157 input/output port 15 input/output programmable input/output port. p160 -p167 input/output port 16 input/output programmable input/output port. p172 -p177 input/output port 17 input/output programmable input/output port. p180 -p187 input/output port 18 input/output programmable input/output port. p190 -p197 input/output port 19 input/output programmable input/output port. p200 -p203 input/output port 20 input/output programmable input/output port. p210 -p217 input/output port 21 input/output programmable input/output port. input/output port (note1) p220 -p227 input/output port 22 input/output programmable input/output port. (however, p93, p97 is an input-only port) note 1: input/output port 5 is reserved for future use.
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 9 outline of the cpu core the 32180 group is built around the m32r risc cpu core, and has the instruction set common to all of the m32r fam- ily microcomputers. to achieve high-precision arithmetic operation, this microcomputer additionally incorporates a fully ieee754 compliant, single-precision fpu. instructions are processed in five pipelined stages consist- ing of instruction fetch, decode, execution, memory access, and write back. thanks to its ?out-of-order-completion? mechanism, the m32r cpu allows clock cycle to realize efficient instruction execution control. the m32r cpu internally contains sixteen 32-bit general- purpose registers. the instruction set consists of 100 dis- crete instructions, which come in either 16-bit or 32-bit in- struction format. use of the 16-bit instruction format helps to reduce the program code size. also, the availability of 32-bit instructions facilitates programming and increases the per- formance at the same clock speed, as compared to archi- tectures with segmented address spaces. multiply-accumulate instructions comparable to dsp the m32r-fpu contains a multiplier/accumulator that can execute 32-bit x 16-bit in one cycle. therefore, it executes a 32-bit x 32-bit integer multiplication instruction in three cy- cles. also, the m32r-fpu supports the following four sum-of- products instructions (or multiplication instructions) for dsp function use. (1) 16 high-order register bits x 16 high-order register bits (2) 16 low-order register bits x 16 low-order register bits (3) all 32 register bits x 16 high-order register bits (4) all 32 register bits x 16 low-order register bits furthermore, the m32r-fpu has instructions for rounding the value stored in the accumulator to 16 or 32-bit, and in- structions for shifting the accumulator value to adjust digits before storing in a register. because these instructions also can be executed in one cycle, dsp comparable data proc- essing capability can be obtained by using them in combi- nation with high-speed data transfer instructions such as load & address update or store & address update. fpu instructions (12 instructions) the m32r-fpu supports single-precision, floating-point arithmetic operations fully compliant with ieee754 standard. more specifically, it supports all of the following five excep- tions and four rounding modes. because the general- purpose registers are used for floating-point arithmetic, data transfer overhead is reduced. five exceptions (invalid operation, division by zero, over- flow, underflow, and precision error) four rounding modes (round toward nearest, round to- ward zero, round toward + , round toward - ) also included are the sum-of-product (fmadd) and differ- ence-of-product (fmsub) instructions suitable for butterfly operation in fft. extended instructions (5 instructions) the m32r-fpu has several instructions implemented in it as extended instructions such as those to set, clear, and test bits, those to set and clear data in the processor status register, and those to automatically increment the address in which to store a halfword. address space the 32180 group?s logical address is always handled in width of 32-bit, providing a linear address space of up to 4g bytes. the 32180 group?s address space is divided into the following spaces. user space a 2g-byte area from h?0000 0000 to h?7fff ffff is the user space. located in this space are the user rom area, external extended area, internal ram area, and sfr (spe- cial function register) area (internal peripheral i/o regis- ters). of these, the user rom area and external extended area are located differently depending on mode settings. system space a 2g-byte area from h?8000 0000 to h?ffff ffff is the system area. this space is reserved for use by develop- ment tools such as an in-circuit emulator and debug monitor, and cannot be used by the user. built-in flash memory and ram the m32180f8vfp, M32180F8TFP group contains 1m bytes (= 1,024k bytes) flash memory and 48k bytes ram. the internal flash memory can be programmed while being mounted on the printed circuit board (on-board program- ming). use of flash memory allows the same chip as those used in mass production to be used beginning with the de- velopment stage. this means that system development can be proceeded without having to change the printed circuit boards during the entire course, from prototype to mass production.
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 10 logical address single-chip mode logical address processor mode external extended mode h?0000 0000 h?0000 0000 16m bytes internal rom (1m bytes) h?000f ffff internal rom h?0010 0000 (16m bytes) h?001f ffff cs0 area cs0 area h?0020 0000 2g bytes user space ghost area in units of 16 bytes h?003f ffff cs1 area cs1 area h?0040 0000 (16m bytes) h?7fff ffff (16m bytes) h?005f ffff cs2 area cs2 area h?8000 0000 h?0060 0000 h?007f ffff cs3 area cs3 area h?0080 0000 sfr area (16k bytes) h?0080 3fff sfr area sfr area h?0080 4000 2g bytes system space ram area (48k bytes) h?0080 ffff ram area ram area h?0081 0000 reserved area (64k bytes) h?0081 ffff reserved area reserved area h?0082 0000 ghost area in units of 128k bytes h?ffff ffff h?00ff ffff *the maximum 8m bytes of extended area figure 4. address space
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 11 +0 address +1 address +0 address +1 address h?0080 0000 h?0080 078c h?0080 078e mjt (tid0) h?0080 0790 h?0080 007e interrupt controller (icu) h?0080 0080 h?0080 07e2 mjt (tou0) multijun ction timer (mjt) h?0080 00ee a-d0 converter h?0080 0a00 h?0080 0100 h?0080 0a26 serial i/o4, 5 h?0080 0146 serial i/o0-3 h?0080 0180 h?0080 0a80 h?0080 0186 wait controller h?0080 0aee ad1 converter h?0080 01e0 h?0080 01f8 flash control h?0080 0b8c h?0080 0b8e mjt (tid1) h?0080 0200 h?0080 0b90 h?0080 023e mjt (common part) h?0080 0be2 mjt (tou1) h?0080 0240 h?0080 02fe mjt (top) h?0080 0300 h?0080 0c8c h?0080 0c8e mjt (tid2) h?0080 0c90 h?0080 03be mjt (tio) h?0080 03c0 h?0080 0ce2 mjt (tou2) h?0080 03d8 mjt (tms) multi- junction timer (mjt) multijun ction timer (mjt) h?0080 03e0 h?0080 03fe mjt (tml0) h?0080 0400 h?0080 0fe0 h?0080 0ffe mjt (tml1) h?0080 0478 dmac h?0080 1000 h?0080 11fe can0 h?0080 0700 h?0080 077f input/output port h?0080 1400 h?0080 15fe can1 figure 5. sfr area
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 12 built-in 64-channel multijunction timers (mjt) the microcomputer contains a total of 64 channels of multijunction timers consisting of 11 channels of 16-bit output related timers, 10 channels of 16-bit input/output related timers, eight channels of 16-bit input related timers, eight channels of 32-bit input related timers, three chan- nels of 16-bit input related up/down-timers, and 24 chan- nels of 24-bit output related timers. each timer has multi- ple operation modes to choose from, depending on the purposes of use. also, the multijunction timers internally have a clock bus, input event bus, and an output event bus, so that multiple timers can be used in combination allowing for a flexible timer configuration. the output related timers have a cor- recting function which allows the timer?s count value to be incremented or decremented as necessary while count is in progress, making real time output control possible. table 3. outline of the mjt name type number of channels contents top (timer out put) output related 16-bit timer (down-counter) 11 one of three output modes is selected in software. single-shot output mode delayed single-shot output mode continuous output mode tio (timer input output) input/output related 16-bit timer (down- counter) 10 one of three input modes and four output modes is selected in software. measure clear input mode measure free-run input mode noise processing input mode pwm output mode single-shot output mode delayed single-shot output mode continuous output mode tms (timer measure small) input related 16-bit timer (up-counter) 8 16-bit input measure timer. tml (timer measure large) 32-bit timer (up-counter) 8 32-bit input measure timer. tid (timer input derivation) input related 16-bit timer (up/down-counter) 3 one of three input modes is selected in software. fixed period mode event count mode up/down event count mode multiply-by-4 event count mode one of five output modes is selected in software. pwm output mode (note1) single-shot pwm mode (note1) delayed one-shot output mode single-shot output mode continuous output mode tou (timer output unification) output related 24-bit timer (down-counter) 24 note 1: during pwm and one-shot pwm modes functions as a 16-bit timer
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 13 interrupt output interrupt output topin note: this is a conceptual diagram and does not show the actual timer configuration. : edge/level selector : prescaler : junction box (selector) : output flip-flop to dma and a-d converter topin tclk pin 1/2 internal peripheral clock tn pin clock bus input event bus 16-bit output related timer: 11 channels 16-bit input/output related timer: 10 channels 16-bit input related timer: 8 channels 16-bit input related up/down timer: 3 channels 24-bit output related timer: 24 channels 32-bit input related timer: 8 channels timer timer output event bus clk clk en en e/l e/l prs f/f f/f e/l prs f/f figure 6. conceptual diagram of the multijunction timers (mjt)
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 14 tclk0 (p124) tin0 (p150) bclk/2 tin1 (p151) tin2 (p152) tin3 (p153) tin4 (p154) tin5 (p155) tin6 (p156) tclk1 (p125) tin7 (p157) tclk2 (p126) tin8 (p140) tin9 (p141) tin10 (p142) tin11 (p143) to0 (p110) to1 (p111) to2 (p112) to3 (p113) to4 (p114) to5 (p115) to6 (p116) to7 (p117) to8 (p100) to9 (p101) to10 (p102) to11 (p103) to12 (p104) to13 (p105) to14 (p106) to15 (p107) to16 (p93) to17 (p94) to18 (p95) to19 (p96) to20 (p97) irq9 dma3,dma irq9 dma6 irq9 dma7 irq12 dma1 irq12 irq12 irq12 irq8 dma8 irq8 dma9 irq8 irq8 irq8 irq2 irq2 irq2 irq2 irq2 irq2 irq1 irq1 irq6 irq6 irq5 irq0 irq0 irq0 irq0 irq4 irq4 irq4 irq4 dma0 dma commonness irq3 irq3 : prescaler : output flip-flop : selector s f/f prs0-5 commonness top 0 clk en udf top 1 clk en udf top 2 clk en udf top 3 clk en udf top 4 clk en udf top 5 clk en udf top 6 clk en udf top 7 clk en udf top 8 clk en udf top 9 clk en udf top 10 clk en udf tio 0 clk en/cap udf tio 1 clk en/cap udf tio 2 clk en/cap udf tio 3 clk en/cap udf tio 4 clk en/cap udf tio 5 clk en/cap udf tio 6 clk en/cap udf tio 7 clk en/cap udf tio 8 clk en/cap udf tio 9 clk en/cap udf s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s tin0s tclk0s f/f10 f/f11 f/f12 f/f13 f/f14 f/f15 f/f16 f/f17 f/f18 f/f19 f/f20 f/f0 f/f1 f/f2 f/f3 f/f4 f/f5 f/f6 f/f7 f/f8 f/f9 tin1s tin2s tin3s tin4s tin5s tin6s s s s prs0 prs1 prs2 tclk1s tin7s tclk2s tin8s tin9s tin10s tin11s s s s 3210 3210 0123 3210 3210 0123 clock bus input event bus output event bus note : irq0-18 denote interrupt signals, with the same number representing interrupts in the same group. dma0-9 and dma common denote dma requests to the dmac. ad0trg and ad1trg denote trigger signals for the a-d0 and a-d1 converters, respectively. figure 7. block diagram of mjt (1/4)
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 15 tclk3 (p127) tin12 (p144) tin13 (p145) tin14 (p146) tin15 (p147) tin16/pwmoff0 (p130) tin17/pwmoff1 (p131) tin18 (p132) tin19 (p133) bclk/2 tin20 (p134) tin21 (p135) tin22 (p136) tin23 (p137) bclk/2 tin30 (p194) tin31 (p195) tin32 (p196) tin33/pwmoff2 (p197) irq10 irq10 dma1 irq10 irq10 irq10 irq10 irq10 dma2 irq10 dma4 irq11 dma5 irq11 irq11 irq11 (to a-d0 converter) ad0trg (to a-d1 converter) ad1trg irq18 irq18 irq18 irq18 ad0trg( to a-d0 converter )/ad1trg( to a-d1 converter ) ad0trg( to a-d0 converter )/ad1trg( to a-d1 converter ) ad0trg (to a-d0 converter) irq7 irq7 tms 0 clk cap3 cap2 cap1 cap0 ovf s tin12s tin13s tin14s tin15s tclk3s s s s s tms 1 clk cap3 cap2 cap1 cap0 ovf tin16s tin17s tin18s tin19s s s s s s tml 0(32bit) clk cap3 cap2 cap1 cap0 tin20s tin21s tin22s tin23s s s s s s tml 1(32bit) clk cap3 cap2 cap1 cap0 tin30s tin31s tin32s tin33s s s s s s 3210 3210 0123 3210 3210 0123 clock bus input event bus output event bus figure 8. block diagram of mjt (2/4)
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 16 tin16/pwmoff0 (p130) bclk/2 tin24 (p172) tin25 (p173) tin17/pwmoff1 (p131) bclk/2 tin26 (p190) tin27 (p191) tin33/pwmoff2 (p197) bclk/2 tin28 (p192) tin29 (p193) to21 (p160) to22 (p161) to23 (p162) to24 (p163) to25 (p164) to26 (p165) to27 (p166) to28 (p167) to29 (p180) to30 (p181) to31 (p182) to32 (p183) to33 (p184) to34 (p185) to35 (p186) to36 (p187) to37 (p210) to38 (p211) to39 (p212) to40 (p213) to41 (p214) to42 (p215) to43 (p216) to44 (p217) irq11 irq11 irq11 irq11 irq11 irq11 dma5 dma6 dma7 dma8 dma9 dma0 dma4 dma1 dma5 dma2 irq13 irq13 irq13 irq13 irq13 irq13 irq13 irq13 irq14 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq15,ad1trg (to a-d1 converter) irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq17 tou0_0 (24-bit) clk en udf tou0_1 (24-bit) clk en udf tou0_2 (24-bit) clk en udf tou0_3 (24-bit) clk en udf tou0_4 (24-bit) clk en udf tou0_5 (24-bit) clk en udf tou0_6 (24-bit) clk en udf tou0_7 (24-bit) clk en udf tid 0 clk clk1 clk2 ovf udf tou1_0 (24-bit) clk en udf tou1_1 (24-bit) clk en udf tou1_2 (24-bit) clk en udf tou1_3 (24-bit) clk en udf tou1_4 (24-bit) clk en udf tou1_5 (24-bit) clk en udf tou1_6 (24-bit) clk en udf tou1_7 (24-bit) clk en udf tid 1 clk clk1 clk2 ovf udf tou2_0 (24-bit) clk en udf tou2_1 (24-bit) clk en udf tou2_2 (24-bit) clk en udf tou2_3 (24-bit) clk en udf tou2_4 (24-bit) clk en udf tou2_5 (24-bit) clk en udf tou2_6 (24-bit) clk en udf tou2_7 (24-bit) clk en udf tid 2 clk clk1 clk2 ovf udf f/f37 f/f38 f/f39 f/f40 f/f41 f/f42 f/f43 f/f44 tin25s pwmoff1s pwmoff2s pwmoff0s po1dis po2dis po0dos tin24s prs3 f/f29 f/f30 f/f31 f/f32 f/f33 f/f34 f/f35 f/f36 f/f21 f/f22 f/f23 f/f24 f/f25 f/f26 f/f27 f/f28 s tin27s tin26s prs4 s tin29s tin28s prs5 s s s s output event bus 0 figure 9. block diagram of mjt (3/4)
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 17 s s s s s s s s s s s dma0 udf end dma1 udf end dma2 udf end dma3 udf end dma4 udf end dma5 udf end dma6 udf end dma7 udf end dma8 udf end dma9 udf end s s s s s s s s s ad0 completed tio8_udf tin0s tid0_udf/ovf can0_s0/s15 tin3s tid1_udf/ovf ad0 completed tio8_udf started in software tin13s started in software tin18s started in software sio0_txd sio1_rxd started in software sio0_rxd started in software started in software dma0-4 interrupt dma5-9 interrupt sio2_rxd sio1_txd tin1s started in software sio2_txd tin2s started in software sio3_rxd started in software sio3_txd tin8s started in software can0_s1/s14 tid2_udf/ovf tin0s ad1 completed tin19s sio0_txd tou1_7irq tin20s tou0_0irq tou2_7irq tou0_1irq sio1_rxd sio3_txd tou0_2irq tou0_6irq tin7s ad1 completed tou0_7irq 0123 input event bus output event bus 3210 3210 0123 figure 10. block diagram of mjt (4/4)
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 18 built-in 10-channel dmac the microcomputer contains 10 channels of dmac, allow- ing for data transfer between internal peripheral i/os, be- tween internal ram and internal peripheral i/o, and be- tween internal rams. dma transfer requests can be issued from the user-created software, as well as can be triggered by a signal generated by the internal peripheral i/o (a-d converter, timer, or serial i/o). the microcomputer also supports cascaded connection between dma channels (starting dma transfer on a chan- nel at end of transfer on another channel). this makes ad- vanced transfer processing possible without causing any additional cpu load. table 4. outline of the dmac item content number of channels 10 channels transfer request software trigger request from internal peripheral i/o: a-d converter, timer, or serial i/o (reception com- pleted, transmit buffer empty) cascaded connection between dma channels possible (note1) maximum number of times transferred 65536 times transferable address space 64k bytes (address space from h?0080 0000 to h?0080 ffff) transfers between internal peripheral i/os, between internal ram and internal peripheral io, and between internal rams are supported transfer data size 16-bit or 8-bit transfer method single transfer dma (control of the internal bus is relinquished for each transfer per- formed), dual-address transfer transfer mode single transfer mode direction of transfer one of three modes can be selected for the source and destination of transfer: address fixed address increment 32-channel ring buffer channel priority channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (fixed priority) maximum transfer rate 13.3m bytes per second (when internal peripheral clock = 20 mhz) interrupt request group interrupt request can be generated when each transfer count register underflows note 1: the following dma channels can be cascaded. dma transfer on channel 1 started at end of one dma transfer on channel 0 dma transfer on channel 5 started at completion of all dma transfers on channel 0 (transfer count register underflow) dma transfer on channel 2 started at end of one dma transfer on channel 1 dma transfer on channel 0 started at end of one dma transfer on channel 2 dma transfer on channel 3 started at end of one dma transfer on channel 2 dma transfer on channel 4 started at end of one dma transfer on channel 3 dma transfer on channel 6 started at end of one dma transfer on channel 5 dma transfer on channel 7 started at end of one dma transfer on channel 6 dma transfer on channel 5 started at end of one dma transfer on channel 7 dma transfer on channel 8 started at end of one dma transfer on channel 7 dma transfer on channel 9 started at end of one dma transfer on channel 8
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 19 s s s s s s s s s s s dma0 udf end dma1 udf end dma2 udf end dma3 udf end dma4 udf end dma5 udf end dma6 udf end dma7 udf end dma8 udf end dma9 udf end s s s s s s s s s ad0 completed tio8_udf tin0s tid0_udf/ovf can0_s0/s15 tin3s tid1_udf/ovf ad0 completed tio8_udf started in software tin13s started in software tin18s started in software sio0_txd sio1_rxd started in software sio0_rxd started in software started in software dma0-4 interrupt dma5-9 interrupt sio2_rxd sio1_txd tin1s started in software sio2_txd tin2s started in software sio3_rxd started in software sio3_txd tin8s started in software can0_s1/s14 tid2_udf/ovf tin0s ad1 completed tin19s sio0_txd tou1_7irq tin20s tou0_0irq tou2_7irq tou0_1irq sio1_rxd sio3_txd tou0_2irq tou0_6irq tin7s ad1 completed tou0_7irq 0123 input event bus output event bus 3210 3210 0123 figure 11. block diagram of dmac
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 20 built-in two independent 16-channel a-d converters the microcomputer contains two 16-channel a-d convert- ers with 10-bit resolution (a-d0 converter and a-d1 con- verter). in addition to single conversion on each channel, continuous a-d conversion on a combined group of n (n = 1?16) channels is possible. the a-d converted value can be read out in either 10-bit or 8-bit. in addition to ordinary a-d conversion, the converters sup- port comparator mode in which the set value and a-d con- verted value are compared to determine which is larger or smaller than the other. moreover, there is also sample & hold mode, input voltage is sampled, when a-d conversion is started, and the a-d conversion of the sampling voltage is carried out. since there is no invalid domain near [which becomes a prob- lem by the external operational amplifier etc.] vcce/vss, con- version by the full range is possible in this sample & hold cir- cuit. when a-d conversion is finished, the converters can gen- erated a dma transfer request, as well as an interrupt. the a-d converters are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5 v. table 5. outline of the a-d converters item content analog input 16-channel x 2 a-d conversion method successive approximation method resolution 10-bit (conversion results can be read out in either 10 or 8-bit) during low speed mode: normal mode: + 2 lsb, double speed mode: + 2 lsb (note1) absolute accuracy (conditions: ta = 25c, avcc0, 1 = vref0, 1 = 5.12 v) during high speed mode: normal mode: + 3 lsb, double speed mode: + 3 lsb (note1) conversion mode a-d conversion mode, comparator mode operation mode single mode, scan mode scan mode single -shot scan mode, continuous scan mode special mode single mode forcible execution under scan mode operation, scan mode start after the sin- gle mode execution, conversion re-start sample & hold mode input voltage is sampled when a-d conversion is started, and it is a-d conversion about sampling voltage. software start started by setting a-d conversion start bit to 1 conversion start trigger hardware start a-d0 conversion start sources: mjt input event bus 2, mjt input event bus 3, mjt output event bus 3, and tin23 a-d1 converter start sources: mjt input event bus 2, mjt input event bus 3, and tid1_ovf / udf / tin23s normal 299bclk 14.95 s (note2) low-speed mode double speed 173bclk 8.65 s normal 131bclk 6.55 s conversion bclk : internal peripheral clock during single mode at the time of sample & hold invalid at the time of normal sample & hold effective high-speed mode double speed 89bclk 4.45 s normal 191bclk 9.55 s low-speed mode double speed 101bclk 5.05 s normal 95bclk 4.75 s during single mode (available for high-speed sample & hold) high-speed mode double speed 53bclk 2.65 s normal 47bclk 2.35 s low-speed mode double speed 29bclk 1.45 s normal 23bclk 1.15 s during comparator mode high-speed mode double speed 17bclk 0.85 s when a-d conversion is finished, when comparate operation is finished interrupt request generation when single-shot scan is finished, or when one cycle of continuous scan is finished when a-d conversion is finished, when comparate operation is finished dma transfer request genera- tion when single-shot scan is finished, or when one cycle of continuous scan is finished note 1: the performance is the same during sample & hold mode. note 2: internal peripheral clock (bclk) = o'clock (1bclk=50ns) of 20mhz conversion time
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 21 ad0in0 ad0in1 ad0in2 ad0in3 ad0in4 ad0in5 ad0in6 ad0in7 selector interrupt request avss0 vref0 10-bit a-d successive approximation register (ad0sar) 10-bit a-d0 data register 0 10-bit a-d0 data register 1 10-bit a-d0 data register 2 10-bit a-d0 data register 3 10-bit a-d0 data register 4 10-bit a-d0 data register 5 10-bit a-d0 data register 6 10-bit a-d0 data register 7 10-bit a-d0 data register 8 10-bit a-d0 data register 9 10-bit a-d0 data register 10 10-bit a-d0 data register 11 10-bit a-d0 data register 12 10-bit a-d0 data register 13 10-bit a-d0 data register 14 10-bit a-d0 data register 15 a-d0 single mode register a-d comparate data register a-d control circuit mode selection channel selectikon conversion time selection flag control interrupt control 10-bit d-a converter comparator ad0in8 ad0in9 ad0in10 ad0in11 ad0in12 ad0in13 ad0in14 ad0in15 ad0cmp ad0dt0 ad0dt1 ad0dt2 ad0dt3 ad0dt4 ad0dt5 ad0dt6 ad0dt7 ad0dt8 ad0dt9 ad0dt10 ad0dt11 ad0dt12 ad0dt13 ad0dt14 ad0dt15 dma transfer request a-d0 scan mode register ad0scm0,1 ad0sim0,1 avcc0 10-bit readout input event bus3 input event bus2 output event bus3 tin23 s s ad0ctrg1 ad0strg1 dma0 dma commonness internal date bus 8-bit readout shifter successive approximationtype a-d converter unit sample & hold control circuit figure 12. block diagram of the a-d0 converter
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 22 ad1in0 ad1in1 ad1in2 ad1in3 ad1in4 ad1in5 ad1in6 ad1in7 selector avss1 vref1 10-bit a-d successive approximation register (ad1sar) 10-bit a-d1 data register 0 a-d comparate data register 10-bit d-a converter comparator ad1in8 ad1in9 ad1in10 ad1in11 ad1in12 ad1in13 ad1in14 ad1in15 ad1cmp ad1dt0 ad1dt1 ad1dt2 ad1dt3 ad1dt4 ad1dt5 ad1dt6 ad1dt7 ad1dt8 ad1dt9 ad1dt10 ad1dt11 ad1dt12 ad1dt13 ad1dt14 ad1dt15 successive approximationtype a-d converter unit ad1scm0,1 ad1sim0,1 avcc1 10-bit readout 8-bit readout shifter s s ad1ctrg1 ad1strg1 input event bus3 input event bus2 tid1_udf/ovf dma3 dma9 tin23s 10-bit a-d1 data register 1 10-bit a-d1 data register 2 10-bit a-d1 data register 3 10-bit a-d1 data register 4 10-bit a-d1 data register 5 10-bit a-d1 data register 6 10-bit a-d1 data register 7 10-bit a-d1 data register 8 10-bit a-d1 data register 9 10-bit a-d1 data register 10 10-bit a-d1 data register 11 10-bit a-d1 data register 12 10-bit a-d1 data register 13 10-bit a-d1 data register 14 10-bit a-d1 data register 15 a-d control circuit mode selection channel selectikon conversion time selection flag control interrupt control dma transfer request interrupt request a-d1 single mode register a-d1 scan mode register internal data bus sample & hold control circuit figure 13. block diagram of the a-d1 converter
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 23 6-channel high-speed serial i/os the microcomputer contains six channels of serial i/os consisting of four channels that can be set for csio mode (clock-synchronized serial i/o) or uart mode (asynchro- nous serial i/o) and two other channels that can only be set for uart mode. the sio has the function to generate a dma transfer re- quest when data reception is completed or the transmit register becomes empty, and is capable of high-speed serial communication without causing any additional cpu load. table 6. outline of the serial i/o item content number of channels csio/uart : 4 channels (sio0, sio1, sio4, sio5) uart only : 2 channels (sio2, sio3) clock during csio mode : internal clock / external clock, selectable (note1) during uart mode: internal clock only transfer mode transmit half-duplex, receive half-duplex, transmit/receive full-duplex brg count source f(bclk), f(bclk)/8, f(bclk)/32, f(bclk)/256 (when internal clock is selected) (note2) data format csio mode: data length = fixed to 8-bit order of transfer = fixed to lsb first uart mode: start bit = 1-bit character length = 7, 8, or 9-bit parity bit = with or without (if included, selectable between odd and even parity) stop bit = 1 or 2-bit order of transfer = fixed to lsb first baud rate csio mode : 152-bit per second to 2m-bit per second (when operating with f(bclk) = 20 mhz) uart mode: 19-bit per second to 156k-bit per second (when operating with f(bclk) = 20 mhz) error detection csio mode : overrun error only uart mode: overrun, parity, and framing errors (the error-sum bit indicates which error has occurred) fixed cycle clock output function when sio0, sio1, sio4, or sio5 is in uart mode, this function outputs a 1/2 brg clock from the sclk pin. note 1: during csio mode, the maximum input frequency of an external clock is f(bclk) divided by 16. note 2: when f(bclk) is selected for the brg count source, the brg set value is subject to limitations.
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 24 sclki0 / sclko0 bclk, bclk/8, bclk/32, bclk/256 baud rate generator (brg) bclk (set value + 1) 1 internal data bus csio mode when internal clock selected csio mode uart mode when internal clock selected 1/16 1/2 rxd0 txd0 receive interrupt transmit /receive control circuit receive dma transfer request transmit interrupt transmit dma transfer request to dma3, dma4 sio0 receive buffer register when external clock selected when uart mode selected note 2: sio2 and sio3 do not have the sclki/sclko function. note 1: when bclk is selected for the brg count source,the brg set value is subject to limitations. sclki1 / sclko1 to dma6 to interrupt controller to interrupt controller to interrupt controller sio0 sio1 sio2 sio3 rxd1 txd1 sio1 transmit shift register sio1 receive shift register to dma7 rxd2 txd2 sio2 transmit shift register sio2 receive shift register to dma9, dma7 rxd3 txd3 sio3 transmit shift register sio3 receive shift register receive interrupt receive interrupt receive dma transfer request receive dma transfer request transmit interrupt transmit interrupt transmit dma transfer request transmit dma transfer request receive interrupt receive dma transfer request transmit interrupt receive interrupt transmit interrupt receive interrupt transmit interrupt transmit dma transfer request to interrupt controller to dma8 to dma5 to dma3, dma6 to dma4 sio4 rxd4 txd4 sio4 transmit shift register sio4 receive shift register sio5 rxd5 txd5 sio5 transmit shift register sio5 receive shift register sclki4 / sclko4 sclki5 / sclko5 sio0 transmit buffer register sio0 transmit shift register sio0 receive shift register clock divider transmit /receive control circuit transmit /receive control circuit transmit /receive control circuit transmit /receive control circuit transmit /receive control circuit figure 14. block diagram of serial i/o
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 25 input/output ports the microcomputer has a total of 158 input/output ports (of which p5 is reserved for future use). the input/output ports can be used as input ports or output ports by setting up their direction registers. each input/output port is a dual- function pin shared with other internal peripheral i/o or ex- ternal extended bus signal lines. these pin functions are selected by using the chip operation mode select or the input/output port operation mode registers table7. outline of input/output ports item specification number of port total 158 ports p0 p1 p2 p3 p4 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 : : : : : : : : : : : : : : : : : : : : : : p00-p07 p10-p17 p20-p27 p30-p37 p41-p47 p61-p63, p65-p67 p70-p77 p82-p87 p93-p97 p100-p107 p110-p117 p124-p127 p130-p137 p140-p147 p150-p157 p160-p167 p172-p177 p180-p187 p190-p197 p200-p203 p210-p217 p220-p227 (8 lines) (8 lines) (8 lines) (8 lines) (7 lines) (6 lines) (8 lines) (6 lines) (5 lines) (8 lines) (8 lines) (4 lines) (8 lines) (8 lines) (8 lines) (8 lines) (6 lines) (8 lines) (8 lines) (4 lines) (8 lines) (8 lines) port function the input/output ports can be set for input or output mode bit wise by using the input/output port direction control register. (however, p221 and p223 are can0 input-only ports.) pin function dual-functions shared with peripheral i/o or external extended signals (or multi-functions shared with periph- eral i/os which have multiple functions) pin function changeover p0-4, p224-p227 : changed by setting cpu operation mode (mod0 and mod1 pins) (note1) p6-22 : changed by setting the input/output port operation mode register (however, peripheral i/o pin functions are selected using the peripheral i/o register.) note 1: when the cpu is operating in external extension mode, p0-p3, p44-p47 and p224-p227 by default are set for in- put/output port pins, but have their functions switched for external extension signal pins by setting the port operation mode register. when operating in single-chip or processor mode, the pin functions are switched over by setting the cpu operation mode pins as shown in table 8. three operation modes 32180 group has three-operation modes-single-chip mode, extended external mode, and processor mode. each operation mode switches over by setting the mod0 and mod1 pins. table 8. cpu operation modes and p0?p4, p224?p227 pin functions mod0 mod1 operation mode p0-p3, p44-p47, p224-p227 pin function vss vss single-chip mode input/output port pin vss vcce external extended mode input/output port pin or external extended signal pin vcce vss processor mode (fp pin = vss) external extended signal pin vcce vcce do not select - note: vcc and vss are connected to power supply and gnd, respectively.
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 26 0 1 2 3 4 5 6 7 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 settings of input/ output port operation mode register reserved settings of chip operation mode (note1) (note1) db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 a23 a24 a25 a26 a27 a28 a29 a30 a15 a16 a17 a18 a19 a20 a21 a22 to16 to17 to18 to19 to20 to9 / to10 / to8 to11 to12 to13 to14 to15 txd3 (note2) ctx1 (note2) a11 / a12 / ctx0 crx0 ctx1 crx1 cs2# cs3# cs2# (note2) cs3# (note2) to0 to1 to2 to3 to4 to5 to6 to7 tclk0 tclk1 tclk2 tclk3 tin0 tin1 tin2 tin3 tin4 tin5 tin6 tin7 to21 to22 to23 to24 to25 to26 to27 to28 to29 to30 to31 to32 to33 to34 to35 to36 tin33/ tin26 tin27 tin28 tin29 tin30 tin31 tin32 pwmoff2 txd4 rxd4 txd5 rxd5 to37 to38 to39 to40 to41 to42 to43 to44 tin8 tin9 tin10 tin11 tin12 tin13 tin14 tin15 tin24 tin25 txd2 rxd2 txd3 rxd3 mod0 mod1 sclki0 / sclki1 / txd0 rxd0 txd1 rxd1 (note3) (note3) sclko0 sclko1 blw# / bhw# / rd# cs0# cs1# a13 a14 ble# bhe# bclk / wait# hreq# hack# rtdtxd rtdrxd rtdack rtdclk wr# sbi# sclki4 / sclki5 / (p61) (p62) (p63) (p67) (note3) sclko4 sclko5 tin16/ tin17/ tin18 tin19 tin20 tin21 tin22 tin23 pwmoff0 pwmoff1 note 1: it changes to an external extension signal pin function at the time of processor mode. at the time of external extension mode, only p41-p43 change to an external bus interface pin. since other pins tur n into an input/output ports pin at the time of reset, it is necessary to set the pin to be used as an external bus inter face pin by the port operation mode register. note 2: it is a triple function pin. it is necessary to set up the circumference function to output by the circumference output selection register. note 3: it cannot be used as a function of an input/output ports. the input level of sbi#, mod0, and an mod1 pin can be read. figure15. input/output ports and pin function assignments
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 27 can modules the 32180 group contains two blocks of full-can modules compliant with can specification v2.0b active. the can modules each have 16 slots of message slot. ctx0 crx0 can0 protocol controller ver 2.0b active can0 message slot 0-15 control register can0 global mask register can0 local mask registera can0 local mask registerb can0 extended id register message memory acceptance filtering 16-bit timer can0 time stamp register can0 configuration register can0 slot status register can0 slot interrupt control register can0 rec register can0 tec register can0 error interrupt control register interrupt control circuit can0 transmit/receive &error interrupt data bus (1)message id (2)date code (3)message data (4)time stamp can0 status register can0 control register figure 16. block diagram of the can0 module ctx1 crx1 can1 protocol controller ver 2.0b active can1 message slot 0-15 control register can1 global mask register can1 local mask registera can1 local mask registerb can1 extended id register message memory acceptance filltering 16-bit timer can1 time stamp register can1 configuration register can1 slot status register can1 slot interrupt control register can1 rec register can1 tec register can1 error interrupt control register interrupt control circuit can1 transmit/receive &error interrupt data bus (1)message id (2)date code (3)message data (4)time stamp can1 status register can1 control register figure 17. block diagram of the can1 module
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 28 8-level interrupt controller the interrupt controller controls interrupt requests from each internal peripheral i/o (32 sources) by using eight priority levels assigned to each interrupt source, including interrupts prohibition. in addition to these interrupts, it han- dles system break interrupt (sbi), reserved instruction exception (rie), and address exception (ae) as non- maskable interrupts. wait controller the wait controller supports access to external devices. for access to an external extended area of up to 8m bytes (during external extended or processor mode), the wait controller controls bus cycle extension by inserting zero to seven wait cycles and using external wait# signal input. however, as setup for lead of cs signal / lead of strobe signal / recovery / idol after lead cycle, only operation by "nothing" setup is guaranteed when 0wait is selected. moreover, wait by the external wait input is not received when 0wait is selected. built-in clock frequency multiplier the pll (clock frequency multiplier) multiplies the input clock frequency by 8 to generate the cpu memory clock. for the maximum cpu memory clock frequency of 80 mhz, the input clock frequency is 10.0 mhz. port input threshold level select function the port input threshold level select function selects the port threshold between ttl, cmos, and schmitt as desired. this setting is possible for each group individually. realtime debugger (rtd) the realtime debugger (rtd) provides a function for ac- cessing directly from the outside to the internal ram. it uses a dedicated clock-synchronized serial i/o to commu- nicate with the outside. use of the rtd communicating via dedicated serial lines allows the internal ram to be read out and rewritten without having to halt the cpu. also, it can activate an exclusive rtd interrupt through rtd communication. built-in virtual-flash emulation function the 1m bytes of internal flash memory can have its 4k bytes areas (total 256 banks) replaced with 4k bytes areas of the internal ram (4k bytes x 8). use of this function helps to make the necessary changes and evaluate the changed program during development phase without hav- ing to reset the microcomputer. also, when combined with the real-time debugger, this function enables the data in ram to be rewritten and read out without causing cpu load, making it possible to reduce the program evaluation period. vt+ vt- schmitt peripheral function input port input pin 0.7vcce 0.5vcce 0.35vcce cmos s s s s s wfnsel ptnsel vtnsell threshold input function enable standard input threshold level of peripheral function figure 18. port input threshold level select function
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 29 command address data internal ram m32r cpu 32180 data data data bus(cpu) data bus(rtd) (rtd) virtual-dpram structure real-time debugger r/w without cpu intervention rtdclk rtdrxd rtdtxd rtdack figure 19. conceptual diagram of the real-time debugger (rtd) h'0000 0000 h'0000 1000 s bank 1 (4k bytes) h'0080 4000 s bank 0 (4k bytes) h'0000 2000 s bank 2 (4k bytes) s bank 255 (4k bytes) s bank 254 (4k bytes) h'000f f000 h'000f d000 h'0080 7fff h'0080 8000 h'0080 9000 h'0080 a000 h'0080 b000 h'0080 c000 h'0080 d000 h'0080 e000 h'0080 f000 h'000f e000 4k bytes 4k bytes 4k bytes 4k bytes 4k bytes 4k bytes 4k bytes 4k bytes s bank 253 (4k bytes) figure20. conceptual diagram of the virtual -flash emulation (units 4k bytes)
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 30 cpu instruction set the m32r employs a risc architecture, supporting a total of 83 discrete instructions. (1) load/store instructions perform data transfer between memory and registers. ld load ldb load byte ldub load unsigned byte ldh load halfword lduh load unsigned halfword lock load locked st store stb store byte sth store halfword unlock store unlocked (2) transfer instructions perform register to register transfer or register to immediate transfer. ld24 load 24-bit immediate ldi load immediate mv move register mvfc move from control register mvtc move to control register seth set high-order 16-bit (3) branch instructions used to change the program flow. bc branch on c-bit beq branch on equal beqz branch on equal zero bgez branch on greater than or equal zero bgtz branch on greater than zero bl branch and link blez branch on less than or equal zero bltz branch on less than zero bnc branch on not c-bit bne branch on not equal bnez branch on not equal zero bra branch jl jump and link jmp jump nop no operation (4) arithmetic/logic instructions perform comparison, arithmetic/logic operation, multiplica- tion/division, or shift between registers. comparison cmp compare cmpi compare immediate cmpu compare unsigned cmpui compare unsigned immediate logical operation and and and3 and 3-operand not logical not or or or3 or 3-operand xor exclusive or xor3 exclusive or 3-operand arithmetic operation add add add3 add 3-operand addi add immediate addv add(with overflow checking) addv3 add 3-operand addx add with carry neg negate sub subtract subv subtract (with overflow checking) subx subtract with borrow multiplication/division div divide divu divide unsigned mul multiply rem remainder remu remainder unsigned shift sll shift left logical sll3 shift left logical 3-operand slli shift left logical immediate sra shift right arithmetic sra3 shift right arithmetic 3-operand srai shift right arithmetic immediate srl shift right logical srl3 shift right logical 3-operand srli shift right logical immediate (5) instructions for the dsp function perform 32-bit x 16-bit or 16-bit x 16-bit multiplication or sum-of-products calculation. these instructions also per- form rounding of the accumulator data or transfer between accumulator and general-purpose register. machi multiply-accumulate high-order halfwords maclo multiply-accumulate low-order halfwords macwhi multiply-accumulate word and high-order halfword macwlo multiply-accumulate word and low-order halfword mulhi multiply high-order halfwords mullo multiply low-order halfwords mulwhi multiply word and high-order halfword mulwlo multiply word and low-order half- word mvfachi move from accumulator high-order word mvfaclo move from accumulator low-order word mvfacmi move from accumulator middle-order word mvtachi move to accumulator high-order word mvtaclo move to accumulator low-order word rac round accumulator rach round accumulator halfword (6) eit related instructions start trap or return from eit processing. rte return from eit trap trap
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r 31 (7) instructions for the fpu function the microcomputer supports fully ieee754 compliant, sin- gle-precision floating-point arithmetic. fadd floating-point add fsub floating-point subtract fmul floating-point multiply fdiv floating-point divide fmadd floating-point multiply and add fmsub floating-point multiply and subtract itof integer to float utof unsigned to float ftoi float to integer ftos float to short fcmp floating-point compare fcmpe floating-point compare with exception if unordered (8) extended instructions sth store halfword(@r+ addressing added) bset bit set bclr bit clear btst bit test setpsw set psw clrpsw clear psw hl h l h l 63 h l h l x x hl x x 32bit 0 0 63 15 16 31 32 47 48 acc rsrc1 rsrc2 mulhi instruction mullo instruction 15 16 31 0151631 0 rsrc1 rsrc2 15 16 31 0151631 0 rsrc1 rsrc2 31 0151631 0 32bit rsrc1 rsrc2 31 0151631 0 063 acc 063 acc 063 acc 063 acc 063 acc mulhi instruction mullo instruction 063 063 acc 0 0 63 63 acc rac instruction sign data sign data rach instruction 031 0313263 acc mvtachi instruction mvtaclo instruction rsrc 0 31 mvfachi instruction mvfacmi instruction mvfaclo instruction rdest 0 0 acc macwhi instruction macwlo instruction machi instruction maclo instruction x x + + x x + + figure 21. instructions for the dsp function
2002-07-12 rev.1.0 mitsubishi microcomputers 32180 group under development single-chip 32-bit cmos microcompute r ?2002 mitsubishi electric corp. new publication, effective jul. 2002. specifications subject to change without notice. mitsubishi electric package dimensions diagram qfp240-p-3232-0.50 weight(g) ? jedec code eiaj package code lead material cu alloy 240p6y-a plastic 240pin 32 x 32mm body qfp ? 0.35 ? ?? 0.45 ? ? ?? ? ? ? ? ? symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 ? ? i 2 1.2 ? ? m d 32.6 ? ? m e 32.6 10 0 0.1 1.3 0.7 0.5 0.3 34.8 34.6 34.4 34.8 34.6 34.4 0.5 32.1 32.0 31.9 32.1 32.0 31.9 0.2 0.15 0.13 0.3 0.2 0.15 3.6 0.25 4.1 e e e e c h e 1 60 61 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 240 120 121 180 181 ?? 0.08 x b x m mmp mitsubishi electric corporation head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit des igns, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer?s application; they do not convey any license under any intellec- tual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party?s rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit applica- tion examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents in formation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended tha t customers contact mitsubishi electric corporation or an authorized mitsubishi semicon- ductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contai ned herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further deta ils on these materials or the products contained therein.
revision history 32180 group data sheet rev. date description page summary (1/1) 1.0 7/12/02 - first edition.

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